Communications between devices that make up an electronic system are typically performed using one or more busses that interconnect such devices. These busses may be dedicated busses coupling only two devices, or they may be used to connect more than two devices. The busses may be formed entirely on a single integrated circuit die, thus being able to connect two or more devices on the same chip. Alternatively, a bus may be formed on a separate substrate than the devices, such as on a printed wiring board.
In computer systems employing advanced architectures and processors, bus transactions typically occur in a pipelined manner. Specifically, the next memory access may start after a previous transaction request is issued; and all components or phases of a bus transaction are not required to complete before another bus transaction may be initiated. Accordingly, requests from numerous bus agents may be pending at any one time. Generally, an arbitration scheme is used to aware bus ownership to a bus agent. However, varying grant-to-valid latencies of the various bus agents may result in unused or wasted bus cycle. As a result, the wasted bus cycles may degrade bus bandwidth and access latency.